In the field of high density interconnect technology, many integrated circuit chips are physically and electrically connected to a single substrate commonly referred to as a multichip module (MCM). To achieve a high wiring and packing density, it is necessary to fabricate a multilayer structure on the substrate to connect integrated circuits to one another. Typically, metal power and ground planes in the substrate are separated by layers of a dielectric such as a polyimide. Embedded in other dielectric layers are metal conductor lines (in the range of about 8 to 25.mu. wide) with vias (holes) providing electrical connections between signal lines or to the metal power and ground planes. Adjacent layers are ordinarily formed so that the primary signal propagation directions are orthogonal to each other. Since the conductor features are typically narrow in width and thick in a vertical direction (in the range of 5 to 10.mu. thick) and must be patterned with microlithography, it is important to produce patterned layers that are substantially flat and smooth (i.e., planar) to serve as the base for the next layer.
If the surface is not flat and smooth, many fabrication problems occur. In a multilayer structure, a flat surface is extremely important to maintain uniform processing parameters from layer to layer. A non-flat surface results in photoresist thickness variations which require pattern or layer dependent processing conditions. The layer dependent processing greatly increases the process complexity and leads to line width variation and reduced yield. Thus, in fabricating multilayer structures, maintaining a flat surface after fabricating each layer allows uniform layer-to-layer processing.
Many approaches to producing a planar surface have been incorporated into methods of fabricating high density interconnects and integrated circuit chips in the past. In one of the oldest methods of fabricating MCMs, referred to herein as the Honeywell approach, vias are plasma etched into the dielectric and a conductive metal (e.g., copper) is sputtered along the sidewalls. This results in a non-planar via which cannot be stacked up from layer to layer and hence a loss of wiring density. Using the Honeywell approach, conductor lines are made by plating or subtractive etching. The lines and vias are planarized by multiple coatings of polyimide which are used to achieve an acceptable degree of planarization. Application of multiple coatings and thick polyimide is time-consuming and creates high stress on the substrate.
In another method, disclosed in U.S. Pat. No. 4,705,606, a via or trench is formed in the dielectric and filled by selective electroplating. This method has the limitation that all of the lines and vias are required to be connected electrically to the periphery of the wafer to carry the electroplating current. This places impractical design constraints on the circuit. The alternative of electroless plating is slow and selective deposition is difficult to achieve. Additional circuit elements that connect the plating feature at one stage of the process and become insulating after uniform or selective heating, such as disclosed in U.S. Pat. No. 4,661,214, add to the process complexity and do not allow passivation of the sidewalls to the conductor features.
Other prior methods have involved plating up features in photoresist patterns, coating them with a very thick polyimide dielectric, and using mechanical polishing to planarize the composite structure. Problems with such methods include: lack of an endpoint detection method for the polishing, incorporation of polishing grit during the process, scratches, mechanical shear stress from polishing, and grit contamination in a clean room. These problems are serious limitations in any practical implementation of such a process.
Integrated circuits, which are fabricated using inorganic dielectric materials (e.g., SiO.sub.2) and much smaller line width dimensions than multichip modules, have used different approaches to produce planar surfaces. These approaches include chemical vapor or spin on deposition of dielectrics. Chemical vapor deposition can leave voids between closely spaced lines and spin deposited dielectrics require multiple complex coatings.
Because of the problems associated with prior attempts to produce planarized surfaces on MCMs and integrated circuit chips, such as those described above, there has remained a need for an effective, rapid, and simple method for planarizing conductors in a dielectric medium.